MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 418

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Queued Analog-to-Digital Converter (QADC)
Technical Data
418
PSA — Prescaler Add Clock Tick Bit
PSL[2:0] — Prescaler Clock Low Time Field
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
The PSL field selects the QCLK low time in the prescaler.
See
To keep the QCLK within the specified range, the PSL field selects the
low time of the QCLK, which can range from one to eight system clock
cycles. The minimum low time for the clock is specified as t
Table 18-4
QCLK low times.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Section 22. Electrical Specifications
Go to: www.freescale.com
displays the bits in PSL field which enable a range of
PSL[2:0]
Table 18-4. Prescaler Clock Low Times
000
001
010
011
100
101
110
111
2 system clock cycles
3 system clock cycles
4 system clock cycles
5 system clock cycles
6 system clock cycles
7 system clock cycles
8 system clock cycles
1 system clock cycle
QCLK Low Time
for f
QCLK
MMC2107 – Rev. 2.0
values.
MOTOROLA
PSL
.