MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 369

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

16.16 Reset
16.17 Interrupts
16.17.1 Transmit Data Register Empty
16.17.2 Transmission Complete
MMC2107 – Rev. 2.0
MOTOROLA
Serial Communications Interface Modules (SCI1 and SCI2)
Reset initializes the SCI registers to a known startup state as described
in
Table 16-10
module.
The TDRE flag is set when the transmit shift register receives a byte from
the SCI data register. It signals that SCIDRH and SCIDRL are empty and
can receive new data to transmit. If the TIE bit in SCICR2 is also set,
TDRE generates an interrupt request. Clear TDRE by reading SCISR1
and then writing to SCIDRL. Reset sets TDRE.
The TC flag is set when TDRE = 1 and no data, preamble, or break
frame is being transmitted. It signals that no transmission is in progress.
If the TCIE bit is set in SCICR2, TC generates an interrupt request.
When TC is set, the TXD pin is idle (logic 1). TC is cleared automatically
when a data, preamble, or break frame is queued. Clear TC by reading
SCISR1 with TC set and then writing to the SCIDRL register. TC cannot
be cleared while a transmission is in progress.
16.7 Memory Map and
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 16-10. SCI Interrupt Request Sources
Go to: www.freescale.com
Transmitter
lists the five interrupt requests associated with each SCI
Receiver
Source
Serial Communications Interface Modules (SCI1 and SCI2)
Registers.
TDRE
RDRF
IDLE
Flag
OR
TC
Enable Bit
TCIE
ILIE
RIE
RIE
TIE
Technical Data
Reset
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