MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 488

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

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Queued Analog-to-Digital Converter (QADC)
18.11.3 Conversion Timing Schemes
Technical Data
488
This section contains some conversion timing examples.
shows the timing for basic conversions where it is assumed that:
Recall that when QS = 0, both queues are disabled, when QS = 8,
queue 1 is active and queue 2 is idle, and when QS = 4, queue 1 is
paused and queue 2 is disabled.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Q1 begins with CCW0 and ends with CCW3.
CCW0 has pause bit set.
CCW1 does not have pause bit set.
External trigger rise edge for Q1.
CCW4 = BQ2 and Q2 is disabled.
Q1 Res shows relative result register updates.
3FE
3FD
3FC
3FB
3FA
3FF
8
7
6
5
4
3
2
1
0
Figure 18-46. Errors Resulting from Clipping
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.010
.020
INPUTS IN VOLTS (V
.030
5.100
RH
= 5.120 V, V
5.110
RL
= 0 V)
5.120
MMC2107 – Rev. 2.0
Figure 18-47
5.130
MOTOROLA