MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 490

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

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Queued Analog-to-Digital Converter (QADC)
18.11.4 Analog Supply Filtering and Grounding
Technical Data
490
Figure 18-48
scan with same assumptions in example 1 except:
When the gate closes and opens again, the conversions start with the
first CCW in Q1.
When the gate closes, the active conversion completes before the
queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
A proposed amended definition for the PF bit in this mode, to reflect the
condition that a gate closing occurred before the queue completed, is
under consideration.
Figure 18-49
continuous scan with the same assumptions as in
At the end of Q1,the completion flag CF1 sets and the queue restarts. If
the queue starts a second time and completes, the trigger overrun flag
TOR1 sets.
Two important factors influencing performance in analog integrated
circuits are supply filtering and grounding. Generally, digital circuits use
bypass capacitors on every V
subsystems or submodules also. Equally important as bypassing is the
distribution of power and ground.
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•
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
No pause bits set in any CCW
External trigger gated mode single scan for Q1
Single scan bit is set.
Go to: www.freescale.com
shows the timing for conversions in gated mode single
shows the timing for conversions in gated mode
DD
/V
SS
pin pair. This applies to analog
Figure
MMC2107 – Rev. 2.0
18-48.
MOTOROLA