MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 285

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

14.6.2.1 PIT Control and Status Register
MMC2107 – Rev. 2.0
MOTOROLA
Address: PIT1 — 0x00c8_0000 and 0x00c8_0001
Reset:
Reset:
PRE[3:0] — Prescaler Bits
PDOZE — Doze Mode Bit
Read:
Read:
Write:
Write:
Programmable Interrupt Timer Modules (PIT1 and PIT2)
The read/write PRE[3:0] bits select the system clock divisor to
generate the PIT clock as
To accurately predict the timing of the next count, change the
PRE[3:0] bits only when the enable bit (EN) is clear. Changing the
PRE[3:0] resets the prescaler counter. System reset and the loading
of a new value into the counter also reset the prescaler counter.
Setting the EN bit and writing to PRE[3:0] can be done in this same
write cycle. Clearing the EN bit stops the prescaler counter.
The read/write PDOZE bit controls the function of the PIT in doze
mode. Reset clears PDOZE.
When doze mode is exited, timer operation continues from the state
it was in before entering doze mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = PIT function stopped in doze mode
0 = PIT function not affected in doze mode
PIT2 — 0x00c9_0000 and 0x00c9_0001
Figure 14-2. PIT Control and Status Register (PCSR)
Bit 15
Bit 7
0
0
0
0
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= Writes have no effect and the access terminates without a transfer error exception.
PDOZE
14
0
0
6
0
PDBG
Programmable Interrupt Timer Modules (PIT1 and PIT2)
13
0
0
5
0
Table 14-2
OVW
12
0
0
4
0
PRE3
shows.
PIE
11
0
3
0
Memory Map and Registers
PRE2
PIF
10
0
2
0
PRE1
RLD
9
0
1
0
Technical Data
PRE0
Bit 8
Bit 0
EN
0
0
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