MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 397

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

17.9 Reset
17.10 Interrupts
17.10.1 SPI Interrupt Flag (SPIF)
17.10.2 Mode Fault (MODF) Flag
MMC2107 – Rev. 2.0
MOTOROLA
Reset initializes the SPI registers to a known startup state as described
in
reset and before writing to the SPIDR register is either indeterminate or
the byte last received from the master before the reset. Reading the
SPIDR after reset returns 0s.
SPIF is set after the eighth SCK cycle in a transmission when received
data transfers from the shift register to SPIDR. If the SPIE bit is also set,
SPIF generates an interrupt request. Once SPIF is set, no new data can
be transferred into SPIDR until SPIF is cleared. Clear SPIF by reading
SPISR with SPIF set and then accessing SPIDR. Reset clears SPIF.
MODF is set when the SS pin of a master SPI is driven low and the SS
pin is configured as a mode-fault input. If the SPIE bit is also set, MODF
generates an interrupt request. A mode fault clears the SPE, MSTR, and
DDRSP[2:0] bits. Clear MODF by reading SPISR with MODF set and
then writing to SPICR1. Reset clears MODF.
Mode fault
Transmission complete
17.7 Memory Map and
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
Interrupt Request
Go to: www.freescale.com
Table 17-8. SPI Interrupt Request Sources
Registers. A transmission from a slave after
Serial Peripheral Interface Module (SPI)
MODF
SPIF
Flag
Enable Bit
Technical Data
SPIE
Reset
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