MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 158

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Interrupt Controller Module
Technical Data
158
ME — Mask Enable Bit
MFI — Mask Fast Interrupts Bit
MASK[4:0] — Interrupt Mask Field
The read/write ME bit enables interrupt masking. Reset clears ME.
The read/write MFI bit enables masking of fast interrupt requests.
Reset clears MFI.
The read/write MASK[4:0] field determines which interrupt priority
levels are masked. When the ME bit is set, all pending interrupt
requests at priority levels at and below the current MASK value are
masked. To mask all normal interrupts without masking any fast
interrupts, set the MASK value to 31 with the MFI bit cleared. See
Table
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Interrupt masking enabled
0 = Interrupt masking disabled
1 = Fast interrupt requests masked by MASK value. All normal
0 = Fast interrupt requests are not masked regardless of the MASK
7-2. Reset clears MASK[4:0].
interrupt requests are masked.
value. The MASK only applies to normal interrupts. Reset
clears MFI.
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Interrupt Controller Module
Decimal
31
0
1
2
3
•
•
•
Table 7-2. MASK Encoding
MASK[4:0]
Binary
00000
00001
00010
00011
11111
•
•
•
Masked Priority
Levels
31–0
1–0
2–0
3–0
0
•
•
•
MMC2107 – Rev. 2.0
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