MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 410

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Queued Analog-to-Digital Converter (QADC)
Technical Data
410
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Access results in the module generating an access termination transfer error if not in test mode.
3. Read/writes have no effect and the access terminates with a transfer error exception.
0x00ca_0014–
0x00ca_0200–
0x00ca_0280–
0x00ca_0300–
0x00ca_0380–
0x00ca_0000
0x00ca_0002
0x00ca_0004
0x00ca_0006
0x00ca_0008
0x00ca_000a
0x00ca_000c
0x00ca_000e
0x00ca_0010
0x00ca_0012
0x00ca_027e
0x00ca_037e
only addresses have no effect and result in a cycle termination transfer error.
0x00ca_01fe
0x00ca_02fe
0x00ca_03fe
Address
MSB
Port QA data register (PORTQA)
Freescale Semiconductor, Inc.
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QADC module configuration register (QADCMCR)
Queued Analog-to-Digital Converter (QADC)
Right justified, unsigned result register (RJURR)
Left justified, unsigned result register (LJURR)
Table 18-2. QADC Memory Map
Left justified, signed result register (LJSRR)
Port QA data direction register (DDRQA)
Conversion command word table (CCW)
QADC test register (QADCTEST)
QADC control register 0 (QACR0)
QADC control register 1 (QACR1)
QADC control register 2 (QACR2)
QADC status register 0 (QASR0)
QADC status register 1 (QASR1)
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Reserved
Reserved
Port QB data register (PORTQB)
(3)
(3)
(2)
LSB
MMC2107 – Rev. 2.0
Access
MOTOROLA
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
—
S
S
(1)