NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 109

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.3.1.6
5.3.2
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
When the LAN controller is in one of the low power states, it searches for a predefined pattern in
the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is
scanned for the entire frame. The LAN controller classifies the incoming packets as one of the
following categories:
Link Status Change Event
The LAN controller link status indication circuit is capable of issuing a PME on a link status
change from a valid link to an invalid link condition or vice versa. The LAN controller reports a
PME link status event in all power states. If the Wake on LAN bit in the EEPROM is not set, the
PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command.
Wake on LAN* (Preboot Wake-Up)
The LAN controller enters Wake on LAN mode after reset if the Wake on LAN bit in the EEPROM
is set. At this point, the LAN controller is in the D0u state. When the LAN controller is in Wake on
LAN mode:
The LAN controller switches from Wake on LAN mode to the D0a power state following a setup of
the Memory or I/O Base Address Registers in the PCI Configuration space.
Serial EEPROM Interface
The serial EEPROM stores configuration data for the ICH6 integrated LAN controller and is a
serial in/serial out device. The LAN controller supports a 64-register or 256-register size EEPROM
and automatically detects the EEPROM’s size. The EEPROM should operate at a frequency of at
least 1 MHz.
All accesses, either read or write, are preceded by a command instruction to the device. The
address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The
end of the address field is indicated by a dummy 0 bit from the EEPROM, which indicates the
entire address field has been transferred to the device. An EEPROM read instruction waveform is
shown in
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No Match: The LAN controller discards the packet and continues to process the incoming
packets.
TCO Packet: The LAN controller implements perfect filtering of TCO packets. After a TCO
packet is processed, the LAN controller is ready for the next incoming packet. TCO packets
are treated as any other wake-up packet and may assert the PME# signal if configured to do so.
Wake-up Packet: The LAN controller is capable of recognizing and storing the first 128 bytes
of a wake-up packet. If a wake-up packet is larger than 128 bytes, its tail is discarded by the
LAN controller. After the system is fully powered-up, software has the ability to determine the
cause of the wake-up event via the PMDR and dump the stored data to the host memory.
Magic Packets are an exception. The Magic Packets may cause a power management event
and set an indication bit in the PMDR; however, it is not stored by the LAN controller for use
by the system when it is woken up.
The LAN controller scans incoming packets for a Magic Packet and asserts the PME# signal
for 52 ms when a 1 is detected in Wake on LAN mode.
The Activity LED changes its functionality to indicates that the received frame passed
Individual Address (IA) filtering or broadcast filtering.
The PCI Configuration registers are accessible to the host.
Figure
5-2.
Functional Description
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