NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 660

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
18.2.14
18.2.15
18.2.16
660
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High Definition Audio Controller Registers (D27:F0)
CORBLBASE—CORB Lower Base Address Register
(Intel
Memory Address: HDBAR + 40h
Default Value:
CORBUBASE—CORB Upper Base Address Register
(Intel
Memory Address: HDBAR + 44h
Default Value:
CORBRP—CORB Write Pointer Register
(Intel
Memory Address: HDBAR + 48h
Default Value:
31:7
31:0
15:8
Bit
6:0
Bit
Bit
7:0
®
®
®
CORB Lower Base Address — R/W. Lower address of the Command Output Ring Buffer, allowing
the CORB base address to be assigned on any 128-B boundary. This register field must not be
written when the DMA engine is running or the DMA transfer may be corrupted.
CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This required the CORB to be
allocated with 128B granularity to allow for cache line fetch optimizations.
CORB Upper Base Address — R/W. Upper 32 bits of the address of the Command Output Ring
buffer. This register field must not be written when the DMA engine is running or the DMA transfer
may be corrupted.
Reserved.
CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this field in
DWord granularity. The DMA engine fetches commands from the CORB until the Read Pointer
matches the Write Pointer. Supports 256 CORB entries (256x4B = 1KB). This register field may be
written while the DMA engine is running.
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
00000000h
00000000h
0000h
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
DWord Size:
Attribute:
Size:
32 bits
32 bits
16 bits
R/W, RO
R/W
R/W