NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 230

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.22.2.1
230
Figure 5-13. AC-Link Protocol
Register Access
Synchronization of all AC-link data transactions is signaled by the AC ’97 controller via the
ACZ_SYNC signal, as shown in
AC-link, which the AC ’97 controller then qualifies with the ACZ_SYNC signal to construct data
frames. ACZ_SYNC, fixed at 48 kHz, is derived by dividing down ACZ_BIT_CLK. ACZ_SYNC
remains high for a total duration of 16 ACZ_BIT_CLK at the beginning of each frame. The portion
of the frame where ACZ_SYNC is high is defined as the tag phase. The remainder of the frame
where ACZ_SYNC is low is defined as the data phase. Each data bit is sampled on the falling edge
of ACZ_BIT_CLK.
The ICH6 has three ACZ_SDIN pins allowing a single, dual, or triple codec configuration. When
multiple codecs are connected, the primary, secondary, and tertiary codecs can be connected to any
ACZ_SDIN line. The ICH6 does not distinguish between codecs on its ACZ_SDIN[2:0] pins,
however the registers do distinguish between ACZ_SDIN[0], ACZ_SDIN[1], and ACZ_SDIN[2]
for wake events, etc. If using a Modem Codec it is recommended to connect it to ACZ_SDIN1.
See your Platform Design Guide for a matrix of valid codec configurations. The ICH6 does not
support optional test modes as outlined in the AC ’97 Specification, Version 2.3.
In the ICH6 implementation of the AC-link, up to three codecs can be connected to the SDOUT
pin. The following mechanism is used to address the primary, secondary, and tertiary codecs
individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits [18:12] of
slot 1 are used for the register index. For I/O writes to the primary codec, the valid bits [14:13] for
slots 1 and 2 must be set in slot 0, as shown in
address, and slot 2 is used to transmit data. For I/O reads to the primary codec, only slot 1 should
be valid since only an address is transmitted. For I/O reads only slot 1 valid bit is set, while for I/O
writes both slots 1 and 2 valid bits are set.
The secondary and tertiary codec registers are accessed using slots 1 and 2 as described above,
however the slot valid bits for slots 1 and 2 are marked invalid in slot 0 and the codec ID bits [1:0]
(bit 0 and bit 1 of slot 0) is set to a non-zero value. This allows the secondary or tertiary codec to
monitor the slot valid bits of slots 1 and 2, and bits [1:0] of slot 0 to determine if the access is
directed to the secondary or tertiary codec. If the register access is targeted to the secondary or
tertiary codec, slot 1 and 2 will contain the address and data for the register access. Since slots 1
and 2 are marked invalid, the primary codec will ignore these accesses.
BIT_CLK
SDIN
SYNC
End of previous
Audio Frame
Codec
Ready
12.288 MHz
slot(1)
("1" = time slot contains valid PCM
Tag Phase
slot(2)
81.4 nS
Time Slot "Valid"
Figure
slot(12)
Bits
"0"
5-13. The primary codec drives the serial bit clock onto the
"0"
Intel
"0"
Table
19
®
Slot 1
I/O Controller Hub 6 (ICH6) Family Datasheet
5-57. Slot 1 is used to transmit the register
0
(48 KHz)
20.8uS
19
Slot 2
Data Phase
0
19
Slot 3
0
19
Slot 12
0