NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 149

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.13.1.4
5.13.1.5
5.13.1.6
5.13.1.7
5.13.2
5.13.2.1
Intel
Table 5-22. NMI Sources
Table 5-23. DP Signal Differences
®
I/O Controller Hub 6 (ICH6) Family Datasheet
NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
Stop Clock Request and Processor Sleep
(STPCLK# and CPUSLP#)
The ICH6 power management logic controls these active-low signals. Refer to
more information on the functionality of these signals.
Processor Power Good (CPUPWRGOOD)
This signal is connected to the processor’s PWRGOOD input. In mobile configurations to allow for
Intel SpeedStep technology support, this signal is kept high during an Intel SpeedStep technology
state transition to prevent loss of processor context. This is an open-drain output signal (external
pull-up resistor required) that represents a logical AND of the ICH6’s PWROK and VRMPWRGD
signals.
Deeper Sleep (DPSLP#) (Mobile Only)
This active-low signal controls the internal gating of the processor’s core clock. This signal asserts
before and de-asserts after the STP_CPU# signal to effectively stop the processor’s clock
(internally) in the states in which STP_CPU# can be used to stop the processor’s clock externally.
Dual-Processor Issues (Desktop Only)
Signal Differences
In dual-processor designs, some of the processor signals are unused or used differently than for
uniprocessor designs.
SERR# goes active (either internally, externally
via SERR# signal, or via message from
(G)MCH)
IOCHK# goes active via SERIRQ# stream
(ISA system Error)
A20M# / A20GATE
STPCLK#
FERR# / IGNNE#
Signal
Cause of NMI
Generally not used, but still supported by Intel
Used for S1 State as well as preparation for entry to S3–S5
Also allows for THERM# based throttling (not via ACPI control methods). Should be
connected to both processors.
Generally not used, but still supported by ICH6.
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h,
bit 11).
Can instead be routed to generate an SCI, through the
NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h,
bit 11).
Difference
®
ICH6.
Comment
Functional Description
Section 5.14
Table
for
5-22.
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