NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 747

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NH82801FBM S L89K

Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801FBM S L89K

Lead Free Status / RoHS Status
Compliant
Intel
Table 22-13. Ultra ATA Timing (Mode 0, Mode 1, Mode 2) (Sheet 1 of 2)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Sym
t83a
t83b
t84a
t84b
t85a
t85b
t86a
t86b
t92a
t92b
t80
t81
t82
t87
t88
t89
t90
t91
Sustained Cycle Time (T2cyctyp)
Cycle Time (Tcyc)
Two Cycle Time (T2cyc)
Data Setup Time (Tds)
Recipient IC data setup time (from
data valid until STROBE edge)
(see Note 2) (Tdsic)
Data Hold Time (Tdh)
Recipient IC data hold time (from
STROBE edge until data may
become invalid) (see Note 2)
(Tdhic)
Data Valid Setup Time (Tdvs)
Sender IC data valid setup time
(from data valid until STROBE
edge) (see Note 2) (Tdvsic)
Data Valid Hold Time (Tdvh)
Sender IC data valid hold time
(from STROBE edge until data
may become invalid) (see Note 2)
(Tdvhic)
Limited Interlock Time (Tli)
Interlock Time w/ Minimum (Tmli)
Envelope Time (Tenv)
Ready to Pause Time (Trp)
DMACK setup/hold Time (Tack)
CRC Word Setup Time at Host
(Tcvs)
CRC word valid hold time at
sender (from DMACK# negation
until CRC may become invalid)
(see Note 2) (Tcvh)
Parameter 1
14.7
72.9
Min
112
230
160
4.8
6.2
6.2
15
70
20
20
20
70
5
9
0
Mode 0
(ns)
240
Max
150
70
50.9
Min
153
125
9.7
4.8
6.2
6.2
73
10
48
20
20
20
48
5
9
0
Mode 1
(ns)
160
Max
150
70
33.9
Min
115
100
6.8
4.8
6.2
6.2
54
31
20
20
20
31
7
5
9
0
Mode 2
Electrical Characteristics
(ns)
120
Max
150
70
Measuring
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Location
Recipient
Recipient
ICH6 ball
Recipient
ICH6 ball
ICH6 ball
ICH6 ball
Recipient
Sender
Sender
Sender
Sender
Note 2
Host
Host
Host
Host
Host
End
Figure
22-10
22-10
22-10
22-10
22-10
22-10
22-12
22-12
22-11
22-12
22-9,
22-9
747

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