NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 541

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

14.1.28
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Power Well:
NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
31:30
29:22
12:6
Bit
Bit
13
21
20
5
4
3
2
1
0
SMI on OS Ownership Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F7:6Ch, bit 29) is 1, the
Reserved — RO. Hardwired to 00h
SMI on Async Advance Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F7:6Ch, bit 21) is a 1, the
SMI on Host System Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F7:6Ch, bit 20) is a 1, the
SMI on Frame List Rollover Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F7:6Ch, bit 19) is a 1,
SMI on Port Change Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F7:6Ch, bit 18) is a 1,
SMI on USB Error Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F7:6Ch, bit 17) is a 1, the host
SMI on USB Complete Enable — R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F7:6Ch, bit 16) is a 1, the
Reserved — RO. Hardwired to 00h
SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.
0 = No Port Owner bit change.
1 = Bits 29:22 correspond to the Port Owner bits for ports 1 (22) through 8 (29). These bits are set
SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.
0 = Power State bits Not modified.
1 = Software modified the Power State bits in the Power Management Control/Status (PMCSR)
SMI on Async — R/WC. Software clears these bits by writing a 1 to it.
0 = No Async Schedule Enable bit change
1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.
host controller will issue an SMI.
host controller will issue an SMI immediately.
host controller will issue an SMI.
the host controller will issue an SMI.
the host controller will issue an SMI.
controller will issue an SMI immediately.
host controller will issue an SMI immediately.
to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to 0.
register (D29:F7:54h).
Suspend
70
00000000h
–
73h
Description
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W, R/WC
32 bits
541