NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 274

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.53
7.1.54
274
HPTC—High Precision Timer Configuration Register
Offset Address:
Default Value:
GCS—General Control and Status Register
Offset Address:
Default Value:
(Desktop)
(Mobile)
31:10
31:8
Bit
6:2
1:0
Bit
7
9
8
7
7
6
Reserved
Address Enable (AE) — R/W.
0 = Address disabled.
1 = The Intel
Reserved
Address Select (AS) — R/W. This 2-bit field selects 1 of 4 possible memory address ranges for
the High Precision Timer functionality. The encodings are:
00 = FED0_0000h–FED0_03FFh
01 = FED0_1000h–FED0_13FFh
10 = FED0_2000h–FED0_23FFh
11 = FED0_3000h–FED0_33FFh
Reserved
Server Error Reporting Mode (SERM) — R/W.
0 = The Intel
1 = The (G)MCH is the final target of all errors from PCI Express* and DMI. In this mode, if the
Reserved
Mobile IDE Configuration Lock Down (MICLD) — R/WLO.
0 = Disabled.
1 = BUC.PRS (offset 3414h, bit 1) is locked and cannot be written until a system reset occurs.
Reserved
FERR# MUX Enable (FME) — R/W. This bit enables FERR# to be a processor break event
indication.
0 = Disabled.
1 = The ICH6 examines FERR# during a C2, C3, or C4 state as a break event.
See
Chapter 5.14.5
1:0 below.
the purpose of generating NMI.
ICH6 detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends
a message to the (G)MCH. If the ICH6 receives an ERR_* message from the downstream
port, it sends that message to the (G)MCH.
This prevents rogue software from changing the default state of the PATA pins during boot
after BIOS configures them. This bit is write once, and is cleared by system reset and when
returning from the S3/S4/S5 states.
3404–3407h
00000000h
3410–3413h
0000000yh y=(00x0x000b)
®
®
ICH6 will decode the High Precision Timer memory address range selected by bits
ICH6 is the final target of all errors. The (G)MCH sends a messages to the ICH for
for a functional description.
Intel
®
Description
Description
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
R/W
32-bit
R/W, R/WLO
32-bit