NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 325

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

9
9.1
.
Intel
Table 9-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0) (Sheet 1 of 2)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: Address locations that are not shown should be treated as Reserved (see
PCI-to-PCI Bridge Registers
(D30:F0)
The ICH6 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements the
buffering and control logic between PCI and the backbone. The arbitration for the PCI bus is
handled by this PCI device.
PCI Configuration Registers (D30:F0)
00–01h
02–03h
04–05h
06–07h
08h
09-0Bh
0Dh
0Eh
18-1Ah
1Bh
1C-1Dh
1E–1Fh
20–23h
24–27h
28–2Bh
2C–2Fh
34h
3C-3Dh
3E–3Fh
40–41h
Offset
CC
BNUM
BCTRL
VID
DID
PCICMD
PSTS
RID
PMLT
HEADTYP
SMLT
IOBASE_LIMIT
SECSTS
MEMBASE_LIMIT
PREF_MEM_BASE
_LIMIT
PMBU32
PMLU32
CAPP
INTR
SPDH
Mnemonic
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Primary Master Latency Timer
Header Type
Bus Number
Secondary Master Latency Timer
I/O Base and Limit
Secondary Status
Memory Base and Limit
Prefetchable Memory Base and Limit
Prefetchable Memory Upper 32 Bits
Prefetchable Memory Limit Upper 32 Bits
Capability List Pointer
Interrupt Information
Bridge Control
Secondary PCI Device Hiding
Register Name
PCI-to-PCI Bridge Registers (D30:F0)
Section 6.2
description.
00000000h
00010001h
00000000h
00000000h
(Desktop)
(ICH6-M)
060401h
000000h
Default
register
8086h
244Eh
2448h
0000h
0010h
0000h
0280h
0000h
0000h
00h
81h
00h
50h
00h
See
for details).
R/WC, RO
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
Type
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
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