NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 147

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.13
5.13.1
5.13.1.1
5.13.1.2
Intel
Warning:
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I/O Controller Hub 6 (ICH6) Family Datasheet
Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The system is booted
Note: The 16-clock counter for INIT# assertion halts while STPCLK# is active. Therefore, if INIT# is
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this
GPI on system boot-up, and manually clear the CMOS array.
with the jumper in new position, then powered back down. The jumper is replaced back to the
normal position, then the system is rebooted again.
Clearing CMOS, using a jumper on VccRTC, must not be implemented.
Processor Interface (D31:F0)
The ICH6 interfaces to the processor with a variety of signals
Most ICH6 outputs to the processor use standard buffers. The ICH6 has separate V_CPU_IO
signals that are pulled up at the system level to the processor voltage, and thus determines V
the outputs to the processor.
Processor Interface Signals
This section describes each of the signals that interface between the ICH6 and the processor(s).
Note that the behavior of some signals may vary during processor reset, as the signals are used for
frequency strapping.
A20M# (Mask A20)
The A20M# signal is active (low) when both of the following conditions are true:
The A20GATE input signal is expected to be generated by the external microcontroller (KBC).
INIT# (Initialization)
The INIT# signal is active (driven low) based on any one of several events described in
When any of these events occur, INIT# is driven low for 16 PCI clocks, then driven high.
supposed to go active while STPCLK# is asserted, it actually goes active after STPCLK# goes
inactive.
This section refers to INIT#, but applies to two signals: INIT# and INIT3_3V#, as INIT3_3V# is
functionally identical to INIT#, but signaling at 3.3 V.
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Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#, IGNNE#,
CPUSLP#, CPUPWRGD
Standard Input from processor: FERR#
Intel SpeedStep
The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
The A20GATE input signal is a 0
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technology output to processor: CPUPWRGOOD (In mobile configurations)
Functional Description
Table
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