NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 639

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

18.1.25
18.1.26
18.1.27
18.1.28
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
MMC—MSI Message Control Register
(Intel
Address Offset:
Default Value:
MMLA—MSI Message Lower Address Register
(Intel
Address Offset:
Default Value:
MMUA—MSI Message Upper Address Register
(Intel
Address Offset:
Default Value:
MMD—MSI Message Data Register
(Intel
Address Offset:
Default Value:
15:8
31:2
31:0
15:0
Bit
6:4
3:1
Bit
1:0
Bit
Bit
7
0
®
®
®
®
Reserved
64b Address Capability (64ADD) — RO. Hardwired to 1. Indicates the ability to generate a 64-bit
message address
Multiple Message Enable (MME) — RO. Normally this is a R/W register. However since only 1
message is supported, these bits are hardwired to 000 = 1 message.
Multiple Message Capable (MMC) — RO. Hardwired to 0 indicating request for 1 message.
MSI Enable (ME) — R/W.
0 = an MSI may not be generated
1 = an MSI will be generated instead of an INTx signal.
Message Lower Address (MLA) — R/W. Lower address used for MSI message.
Reserved.
Message Upper Address (MUA) — R/W. Upper 32-bits of address used for MSI message.
Message Data (MD) — R/W. Data used for MSI message.
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
62h
0080h
64h
00000000h
68h
00000000h
6Ch
0000h
Intel
®
High Definition Audio Controller Registers (D27:F0)
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO, R/W
16 bits
RO, R/W
32 bits
R/W
32 bits
R/W
16 bits
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