NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 401

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.8.1.7
10.8.1.8
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
MSC_FUN—Miscellaneous Functionality Register
(PM—D31:F0)
Offset Address:
Default Value:
Power Well:
GPI_ROUT—GPI Routing Control Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
31:30
Bit
5:4
3:2
1:0
Bit
7:6
1:0
4
5
3
2
GPI15 Route — R/W. See bits 1:0 for description.
GPI2 Route — R/W. See bits 1:0 for description.
GPI1 Route — R/W. See bits 1:0 for description.
GPI0 Route — R/W. GPI[15:0] can be routed to cause an SMI or SCI when the GPI[n]_STS bit is
set. If the GPIO is not set to an input, this field has no effect.
If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPI can cause a
Wake event, even if the GPI is NOT routed to cause an SMI# or SCI.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
10 = SCI (if corresponding GPE0_EN bit is also set)
11 = Reserved
Software must set this bit field to generate the appropriate type of system interrupt, depending on
how the SCI_EN bit is set. For example, if the SCI_EN bit is set, then this field must be programmed
to 00b or 10b. If the SCI_EN bit is cleared, then this field must be programmed to 00b or 01b.
Software must also update this field if the SCI_EN bit is changed.
Reserved
LPC Generic Range 2 Bit 5 Mask (LGR5M) — R/W.
0 = The existing LPC Generic I/O decode range 2 decodes bit 5 as defined in the D31:F0h:88h
1 = The LPC Generic I/O decode range 2 forces an address match on bit 5.
NOTE: If this bit is set, LGR4M (bit 4 of this register) must also be set.
LPC Generic Range 2 Bit 4 Mask (LGR4M) — R/W.
0 = The existing LPC Generic I/O decode range 2 decodes bit 4 as defined in the D31:F0h:88h
1 = The LPC Generic I/O decode range 2 forces an address match on bit 4.
Reserved
Top Swap Status (TSS) — RO. This bit provides a read-only path to view the state of the Top Swap
bit that is in the Chipset Configuration Registers:Offset 3414h:bit 0.
USB Transient Disconnect Detect (TDD) — R/W: This field prevents a short Single-Ended Zero
(SE0) condition on the USB ports from being interpreted by the UHCI host controller as a
disconnect. BIOS should set to 11b.
register description.
register description.
ADh
00h
Resume
B8h – BBh
00000000h
No
Same pattern for GPI14 through GPI3
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Attribute:
Size:
Power Well:
R/W
8-bit
R/W
32-bit
Resume
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