NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 250

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Chipset Configuration Registers
7.1.3
7.1.4
7.1.5
250
VCAP2—Virtual Channel Capability #2 Register
Offset Address:
Default Value:
PVC—Port Virtual Channel Control Register
Offset Address:
Default Value:
PVS—Port Virtual Channel Status Register
Offset Address:
Default Value:
31:24
15:04
15:01
23:0
Bit
Bit
3:1
Bit
0
0
VC Arbitration Table Offset (ATO) — RO. This bit indicates that no table is present for VC
arbitration since it is fixed.
Reserved
Reserved
VC Arbitration Select (AS) — RO. This bit indicates which VC should be programmed in the VC
arbitration table. The root complex takes no action on the setting of this field since there is no
arbitration table.
Load VC Arbitration Table (LAT) — RO. This bit indicates that the table programmed should be
loaded into the VC arbitration table. This bit is defined as read/write with always returning 0 on
reads.
Reserved
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the VC
Arbitration table when it is being updated. This field is always 0 in the root complex since there is
no VC arbitration table.
0008–000Bh
00000001h
000C–000Dh
0000h
000E–000Fh
0000h
Intel
®
Description
Description
Description
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
32-bit
RO
R/W, RO
16-bit
16-bit