NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 485

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

12.2.2
12.2.3
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
BMIS[P,S]—Bus Master IDE Status Register
Address Offset:
Default Value:
BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register
Address Offset:
Default Value:
31:2
Bit
4:3
Bit
1:0
7
6
5
2
1
0
PRD Interrupt Status (PRDIS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit set.
Drive 1 DMA Capable — R/W.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 1 for this
Drive 0 DMA Capable — R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that drive 0 for this
Reserved. Returns 0.
Interrupt — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not disabled
Error — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when the controller encounters a target abort or master abort when transferring
Bus Master IDE Active (ACT) — RO.
0 = This bit is cleared by the ICH6 when the last transfer for a region is performed, where EOT for
1 = Set by the ICH6 when the Start bit is written to the Command register.
Address of Descriptor Table (ADDR) — R/W. The bits in this field correspond to A[31:2]. The
Descriptor Table must be dword-aligned. The Descriptor Table must not cross a 64-K boundary in
memory.
Reserved
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The Intel
BMIDE to the PCI bus.
channel is capable of DMA transfers, and that the controller has been initialized for optimum
performance. The ICH6 does not use this bit. It is intended for systems that do not attach
BMIDE to the PCI bus.
interrupts via the nIEN bit of the Device Control Register (see chapter 5 of the Serial ATA
Specification , Revision 1.0a).
data on PCI.
that region is set in the region descriptor. It is also cleared by the ICH6 when the Start Bus
Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the Command register. When this bit is read
as a 0, all data transferred from the drive during the previous bus master command is visible in
system memory, unless the bus master command was aborted.
(D31:F2)
Primary: BAR + 02h
Secondary: BAR + 0Ah
00h
Primary: BAR + 04h–07h
Secondary: BAR + 0Ch
All bits undefined
®
ICH6 does not use this bit. It is intended for systems that do not attach
–
0Fh
Description
Description
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W, R/WC, RO
8 bits
R/W
32 bits
(D31:F2)
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