NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 5

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
5.6
5.7
5.8
5.9
5.5.1
DMA Operation (D31:F0) ..................................................................................................121
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
LPC DMA..........................................................................................................................124
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
5.7.6
5.7.7
8254 Timers (D31:F0).......................................................................................................128
5.8.1
5.8.2
8259 Interrupt Controllers (PIC) (D31:F0) ........................................................................131
5.9.1
5.9.2
5.9.3
5.9.4
LPC Interface .......................................................................................................116
5.5.1.1
5.5.1.2
5.5.1.3
5.5.1.4
5.5.1.5
5.5.1.6
5.5.1.7
5.5.1.8
5.5.1.9
5.5.1.10 Bus Master Cycles ...............................................................................120
5.5.1.11 LPC Power Management .....................................................................120
5.5.1.12 Configuration and Intel
Channel Priority ...................................................................................................122
5.6.1.1
5.6.1.2
Address Compatibility Mode ................................................................................122
Summary of DMA Transfer Sizes ........................................................................123
5.6.3.1
Autoinitialize.........................................................................................................123
Software Commands ...........................................................................................124
Asserting DMA Requests.....................................................................................124
Abandoning DMA Requests ................................................................................125
General Flow of DMA Transfers ..........................................................................125
Terminal Count ....................................................................................................126
Verify Mode..........................................................................................................126
DMA Request De-assertion .................................................................................126
SYNC Field / LDRQ# Rules .................................................................................127
Timer Programming .............................................................................................128
Reading from the Interval Timer ..........................................................................129
5.8.2.1
5.8.2.2
5.8.2.3
Interrupt Handling ................................................................................................132
5.9.1.1
5.9.1.2
5.9.1.3
Initialization Command Words (ICWx) .................................................................133
5.9.2.1
5.9.2.2
5.9.2.3
5.9.2.4
Operation Command Words (OCW) ....................................................................134
Modes of Operation .............................................................................................134
5.9.4.1
5.9.4.2
5.9.4.3
LPC Cycle Types .................................................................................117
Start Field Definition.............................................................................117
Cycle Type / Direction (CYCTYPE + DIR) ...........................................118
SIZE .....................................................................................................118
SYNC ...................................................................................................119
SYNC Time-Out ...................................................................................119
SYNC Error Indication..........................................................................119
LFRAME# Usage .................................................................................119
I/O Cycles ............................................................................................120
Fixed Priority ........................................................................................122
Rotating Priority ...................................................................................122
Address Shifting When Programmed for 16-Bit
I/O Count by Words .............................................................................123
Simple Read ........................................................................................130
Counter Latch Command .....................................................................130
Read Back Command ..........................................................................130
Generating Interrupts ...........................................................................132
Acknowledging Interrupts.....................................................................132
Hardware/Software Interrupt Sequence...............................................133
ICW1 ....................................................................................................133
ICW2 ....................................................................................................134
ICW3 ....................................................................................................134
ICW4 ....................................................................................................134
Fully Nested Mode ...............................................................................134
Special Fully-Nested Mode ..................................................................135
Automatic Rotation Mode (Equal Priority Devices) ..............................135
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ICH6 Implications..........................................120
Contents
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