NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 705

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

19.1.48
19.1.49
19.1.50
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
PVC—Port Virtual Channel Control Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
PVS — Port Virtual Channel Status Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
V0CAP — Virtual Channel 0 Resource Capability Register
(PCI Express—D28:F0/F1/F2/F3)
Address Offset:
Default Value:
31:24
22:16
15:4
15:1
13:8
Bit
3:1
Bit
Bit
7:0
23
15
14
0
0
Reserved.
VC Arbitration Select (AS) — R/W. This field indicates which VC should be programmed in the VC
arbitration table. The root port takes no action on the setting of this field since there is no arbitration
table.
Load VC Arbitration Table (LAT) — R/W. This bit indicates that the table programmed should be
loaded into the VC arbitration table. This bit always returns 0 when read.
Reserved.
VC Arbitration Table Status (VAS) — RO. This bit indicates the coherency status of the VC
Arbitration table when it is being updated. This field is always 0 in the root port since there is no VC
arbitration table.
Port Arbitration Table Offset (AT) — RO. This VC implements no port arbitration table since the
arbitration is fixed.
Reserved.
Maximum Time Slots (MTS) — RO. This VC implements fixed arbitration, and therefore this field is
not used.
Reject Snoop Transactions (RTS) — RO. This VC must be able to take snoopable transactions.
Advanced Packet Switching (APS) — RO. This VC is capable of all transactions, not just advanced
packet switching transactions.
Reserved.
Port Arbitration Capability (PAC) — RO. This field indicates that this VC uses fixed port arbitration.
10C
0000h
10E
0000h
110
00000001h
–
–
–
113h
10Fh
10Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
PCI Express* Configuration Registers
R/W
16 bits
RO
16 bits
RO
32 bits
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