NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 440

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1)
11.1.4
440
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS — PCI Status Register (IDE—D31:F1)
Address Offset:
Default Value:
effect.
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated by Bus Master IDE interface function.
1 = Bus Master IDE interface function, as a master, generated a master abort.
Reserved as 0 — RO.
Reserved as 0 — RO.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; however, the ICH6 does not have a real DEVSEL# signal associated with the IDE
Data Parity Error Detected (DPED) — RO. Reserved as 0.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Reserved
Interrupt Status (INTS) — RO . This bit is independent of the state of the Interrupt Disable bit in the
command register.
0 = Interrupt is cleared.
1 = Interrupt/MSI is asserted.
NOTE: This bit will read ‘1’ after Power On Reset when no parallel ATA drive is attached. This is
Reserved
unit, so these bits have no effect.
the intended behavior.
06
0280h
–
07h
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/WC, RO
16 bits