NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 642

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
18.1.32
642
®
High Definition Audio Controller Registers (D27:F0)
DEVC—Device Control Register
(Intel
Address Offset:
Default Value:
14:12
Bit
7:5
15
11
10
9
8
4
3
2
1
0
®
Reserved
Max Read Request Size — RO. Hardwired to 0 enabling 128B maximum read request size.
No Snoop Enable (NSNPEN) — R/W.
0 = The Intel High Definition Audio controller will not set the No Snoop bit. In this case, isochronous
1 = The Intel High Definition Audio controller is permitted to set the No Snoop bit in the Requester
Note: This bit is not reset on D3
Auxiliary Power Enable — RO. Hardwired to 0, indicating that Intel High Definition Audio device
does not draw AUX power
Phantom Function Enable — RO. Hardwired to 0 disabling phantom functions.
Extended Tag Field Enable — RO. Hardwired to 0 enabling 5-bit tag.
Max Payload Size — RO. Hardwired to 0 indicating 128B.
Enable Relaxed Ordering — RO. Hardwired to 0 disabling relaxed ordering.
Unsupported Request Reporting Enable — RO. Not implemented. Hardwired to 0.
Fatal Error Reporting Enable — RO. Not implemented. Hardwired to 0.
Non-Fatal Error Reporting Enable — RO. Not implemented. Hardwired to 0.
Correctable Error Reporting Enable — RO. Not implemented. Hardwired to 0.
High Definition Audio Controller—D27:F0)
transfers will not use VC1 (VCi) even if it is enabled since VC1 is never snooped. Isochronous
transfers will use VC0.
Attributes of a bus master transaction. In this case, VC0 or VC1 may be used for isochronous
transfers.
78h
0800h
HOT
to D0 transition; however, it is reset by PLTRST#.
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W, RO
16 bits