NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 340

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI-to-PCI Bridge Registers (D30:F0)
9.1.24
9.1.25
340
BPC—Bridge Policy Configuration Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
SVCAP—Subsystem Vendor Capability Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
15:8
31:7
Bit
7:0
Bit
4:3
6
5
2
1
0
Next Capability (NEXT) — RO. Value of 00h indicates this is the last item in the list.
Capability Identifier (CID) — RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor
capability.
Reserved
PERR#-to-SERR# Enable (PSE) — R/W. When this bit is set, a 1 in the PERR# Assertion status bit
(in the Bridge Proprietary Status register) will result in an internal SERR# assertion on the primary
side of the bridge (if also enabled by the SERR# Enable bit in the primary Command register).
SERR# is a source of NMI.
Secondary Discard Timer Testmode (SDTT) — R/W.
0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E, bit 9)
1 = The secondary discard timer will expire after 128 PCI clocks.
Reserved
Reserved
Reserved
Received Target Abort SERR# Enable (RTAE) — R/W. When set, the PCI bridge will report
SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are set, and
CMD.SEE (D30:F0:04 bit 8) is set.
4C
00000000h
50
000Dh
–
–
51h
4Fh
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
32 bits
RO
16 bits
R/W, RO