NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 540

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
14.1.27
540
LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
Power Well:
NOTE: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
28:22
Bit
31
30
29
21
20
19
18
17
16
15
14
SMI on BAR — R/WC. Software clears this bit by writing a 1 to it.
0 = Base Address Register (BAR) not written.
1 = This bit is set to 1 when the Base Address Register (BAR) is written.
SMI on PCI Command — R/WC. Software clears this bit by writing a 1 to it.
0 = PCI Command (PCICMD) Register Not written.
1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written.
SMI on OS Ownership Change — R/WC. Software clears this bit by writing a 1 to it.
0 = No HC OS Owned Semaphore bit change.
1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP register
Reserved — RO. Hardwired to 00h
SMI on Async Advance — RO. This bit is a shadow bit of the Interrupt on Async Advance bit
(D29:F7:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Interrupt on Async Advance bit in the
SMI on Host System Error — RO. This bit is a shadow bit of Host System Error bit in the
USB2.0_STS register (D29:F7:CAPLENGTH + 24h, bit 4).
NOTE: To clear this bit system software must write a 1 to the Host System Error bit in the
SMI on Frame List Rollover — RO. This bit is a shadow bit of Frame List Rollover bit
(D29:F7:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in the
SMI on Port Change Detect — RO. This bit is a shadow bit of Port Change Detect bit
(D29:F7:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in the
SMI on USB Error — RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT) bit
(D29:F7:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in the
SMI on USB Complete — RO. This bit is a shadow bit of USB Interrupt (USBINT) bit
(D29:F7:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the USB2.0_STS
SMI on BAR Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on BAR (D29:F7:6Ch, bit 31) is 1, then the host controller
SMI on PCI Command Enable — R/W.
0 = Disable.
1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F7:6Ch, bit 30) is 1, then the host
(D29:F7:68h, bit 24) transitions from 1 to 0 or 0 to 1.
will issue an SMI.
controller will issue an SMI.
USB2.0_STS register.
USB2.0_STS register.
USB2.0_STS register.
USB2.0_STS register.
USB2.0_STS register.
register.
Suspend
6C
00000000h
–
6Fh
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W, R/WC, RO
32 bits