NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 758

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
758
Table 22-22. Power Management Timings (Sheet 3 of 3)
NOTES:
10.This value should be at most a few clocks greater than the minimum.
12.The ICH6 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
13.The ICH6 has no maximum timing requirement for this transition. It is up to the system designer to determine
14.If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted
11.This value is programmable in multiples of 1024 PCI clocks. Maximum is 8192 PCI clocks (245.6 µs).
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay
2. The Min/Max times depend on the programming of the “SLP_S4# Minimum Assertion Width” and the
3. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
4. Note that this does not apply for synchronous SMIs.
5. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30ns.
6. If the (G)MCH does not have the CPUSLP# signal, then the minimum value can be 0 µs.
7. This is a clock generator specification
8. This is non-zero to enforce the minimum assert time for DPRSLPVR. If the minimum assert time for
9. This is non-zero to enforce the minimum assert time for STP_CPU#. If the minimum assert time for
Sym
t297
t298
t299
t300
t301
t302
t310
from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.
“SLP_S4# Assertion Stretch Enable bits (D31:F0:A4h bits 5:3).
DPRSLPVR has been met, then this is permitted to be 0.
STP_CPU# has been met, then this is permitted to be 0.
for this cycle getting to the ICH6 is dependant on the processor and the memory controller.
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
together similar to timing t287 (PCIRST# active to SLP_S3# active).
SLP_S5# inactive to SLP_S4# inactive
SLP_S4# inactive to SLP_S3# inactive
S4 Wake Event to SLP_S4# inactive (S4 Wake)
S3 Wake Event to SLP_S3# inactive (S3 Wake)
CPUSLP# inactive to STPCLK# inactive
(Desktop Only)
(S3
ICH6 check for PWROK active
THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
HOT
Configuration Only) SLP_S3# inactive to
Parameter
Other Timings
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Min
1
0
8
4
–
See Note Below
See Note Below
small
possi
Max
ble
as
2
–
5
2
RTCCLK
RTCCLK
PCI CLK
PCICLK
Units
msec
22-23
22-24
22-25
22-26
22-23
22-24
22-25
22-26
22-23
22-24
22-25
22-26
22-23
22-24
22-25
22-26
22-22
22-23
22-24
22-25
22-26
Fig
Notes
2
3
2
3