NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 579

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

15.2.18
15.2.19
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Note: This register is in the resume well and is reset by RSMRST#.
Note: This register is in the resume well and is reset by RSMRST#.
NOTIFY_DLOW—Notify Data Low Byte Register
(SMBus—D31:F3)
Register Offset:
Default Value:
NOTIFY_DHIGH—Notify Data High Byte Register
(SMBus—D31:F3)
Register Offset:
Default Value:
Bit
7:0
Bit
7:0
DATA_HIGH_BYTE — RO. This field contains the second (high) byte of data received during the
Host Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid
when the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1.
DATA_LOW_BYTE — RO. This field contains the first (low) byte of data received during the Host
Notify protocol of the SMBus 2.0 specification. Software should only consider this field valid when
the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1.
SMBASE + 16h
00h
SMBASE + 17h
00h
§
Description
Description
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
RO
8 bits
RO
8 bits
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