NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 487

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

12.3.1.1
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
CAP—Host Capabilities Register (D31:F2)
Address Offset:
Default Value:
All bits in this register that are R/WO are reset only by PLTRST#.
23:20
12:8
Bit
7:5
4:0
31
30
29
28
27
26
25
24
19
18
17
16
15
14
13
Supports 64-bit Addressing (S64A) — RO. This bit indicates that the SATA controller can access
64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the PRD Base, and each
PRD entry are read/write.
Supports Command Queue Acceleration (SCQA) — RO. Hardwired to 1 to indicate that the SATA
controller supports SATA command queuing via the DMA Setup FIS. The Intel
Setup FISes natively, and can handle auto-activate optimization through that FIS.
Supports Cold Presence Detect (SCD) — RO. Cold presence detect not supported.
Supports Interlock Switch (SIS) — R/WO. This bit indicates whether the SATA controller supports
interlock switches on its ports for use in Hot-Plug operations. This value is loaded by platform BIOS
prior to OS initialization.
If this bit is set, BIOS must also map the SATAGP pins to the SATA controller through GPIO space.
Supports Staggered Spin-up (SSS) — R/WO. This bit indicates whether the SATA controller
supports staggered spin-up on its ports, for use in balancing power spikes. This value is loaded by
platform BIOS prior to OS initialization.
0 = Staggered spin-up not supported.
1 = Staggered spin-up supported.
Supports Aggressive Link Power Management (SALP) — R/W.
0 = Indicates that the SATA controller does not support auto-generating link requests to the partial
1 = Indicates that the SATA controller supports auto-generating link requests to the partial or
Note: For only B-1 step devices, BIOS must clear this bit.
Supports Activity LED (SAL) — RO. This field indicates that the SATA controller supports a single
output pin (SATALED#) which indicates activity.
Supports Raw FIS Mode (SRM) — RO. The SATA controller does not support raw FIS mode.
Interface Speed Support (ISS) — RO. This field indicates the maximum speed the SATA controller
can support on its ports.
0h =1.5 Gb/s.
Supports Non-Zero DMA Offsets (SNZO) — RO. Reserved, as per the AHCI Revision 1.0
specification
Supports Port Selector Acceleration — RO. Port Selectors not supported.
Supports Port Multiplier (PMS) — R/WO. ICH6 does not support port multiplier. BIOS/SW shall
write this bit to ‘0’ during AHCI initalization.
Supports Port Multiplier FIS Based Switching (PMFS) — RO. Reserved, as per the AHCI Revision
1.0 specification.
Reserved. Returns 0.
Slumber State Capable (SSC) — RO. The SATA controller supports the slumber state.
Partial State Capable (PSC) — RO. The SATA controller supports the partial state.
Number of Command Slots (NCS) — RO. Hardwired to 1Fh to indicate support for 32 slots.
Reserved. Returns 0.
Number of Ports (NPS) — RO. Hardwired to 3h to indicate support for 4 ports. Note that the number
of ports indicated in this field may be more than the number of ports indicated in the PI (ABAR +
0Ch) register.
or slumber states when there are no commands to process.
slumber states when there are no commands to process.
ABAR + 00h–03h
C6027F03h
Description
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/WO, RO
32 bits
®
ICH6 handles DMA
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