NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 161

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
Table 5-30. Causes of Wake Events
Table 5-31. GPI Wake Events
®
I/O Controller Hub 6 (ICH6) Family Datasheet
NOTES:
It is important to understand that the various GPIs have different levels of functionality when used
as wake events. The GPIs that reside in the core power well can only generate wake events from
sleep states where the core well is powered.
events.
The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply
design, so much so that the exit latencies due to the ICH6 are insignificant.
RTC Alarm
Power Button
GPI[0:15]
Classic USB
LAN
RI#
AC ‘97 / Intel High
Definition Audio
Primary PME#
Secondary PME#
PCI_EXP_WAKE#
PCI_EXP PME
Message
SMBALERT#
SMBus Slave
Message
SMBus Host Notify
message received
1. If in the S5 state due to a powerbutton override or THRMTRIP#, the possible wake events are due to Power
2. When the WAKE# pin is active and the PCI Express device is enabled to wake the system, the ICH6 will
3. This is a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP bits
GPI[15:13,11:8]
GPI[12, 7:0]
Button, Hard Reset Without Cycling (See Command Type 3 in
Command Type 4 in
wake the platform.
via software, or if there is a power failure.
Cause
GPI
1,2
Power Well
Wake From
Resume
States Can
Table
Core
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1–S5
S1
–
–
–
–
–
–
–
–
–
–
–
–
S5
S5
S5
S5
S5
S5
S5
S5
S5
S5
S5
S5
5-52).
3
3
3
3
Set RTC_EN bit in PM1_EN register
Always enabled as Wake event
GPE0_EN register
NOTE: GPIs that are in the core well are not capable of waking the
Set USB1_EN, USB 2_EN, USB3_EN, and USB4_EN bits in GPE0_EN
register
Will use PME#. Wake enable set with LAN logic.
Set RI_EN bit in GPE0_EN register
Set AC97_EN bit in GPE0_EN register
PME_B0_EN bit in GPE0_EN register
Set PME_EN bit in GPE0_EN register.
PCI_EXP_WAKE bit (Note 3)
Must use the PCI Express* WAKE# pin rather than messages for wake
from S3,S4, or S5.
Always enabled as Wake event
Wake/SMI# command always enabled as a Wake event.
Note: SMBus Slave Message can wake the system from S1–S5, as well
as from S5 due to Power Button Override.
HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported
in the SMB_WAK_STS bit in the GPEO_STS register.
Wake From
S1–S5
S1
system from sleep states where the core well is not powered.
Table 5-31
ACPI Compliant
ACPI Compliant
Notes
summarizes the use of GPIs as wake
Table
How Enabled
5-52), and Hard Reset System (See
Functional Description
161