NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 273

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

7.1.51
7.1.52
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
OIC—Other Interrupt Control Register
Offset Address:
Default Value:
RC—RTC Configuration Register
Offset Address:
Default Value:
31:5
Bit
7:2
Bit
1:0
1
0
4
3
2
Reserved
Coprocessor Error Enable (CEN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = If FERR# is low, the Intel
APIC Enable (AEN) — R/W.
0 = The internal IOxAPIC is disabled.
1 = Enables the internal IOxAPIC and its address decode.
Reserved
Upper 128 Byte Lock (UL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed.
Lower 128 Byte Lock (LL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed.
Upper 128 Byte Enable (UE) — R/W.
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
Reserved
write. It will also drive IGNNE# active.
Writes will be dropped and reads will not return any guaranteed data. Bit reset on system
reset.
Writes will be dropped and reads will not return any guaranteed data. Bit reset on system
reset.
31FF–31FFh
00h
3400–3403h
00000000h
®
ICH6 generates IRQ13 internally and holds it until an I/O port F0h
Description
Description
Attribute:
Size:
Attribute:
Size:
Chipset Configuration Registers
R/W
8-bit
R/W, R/WLO
32-bit
273