NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 529

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

14.1.3
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
PCICMD—PCI Command Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit (D29:F7:06h, bit 3) is not affected by the interrupt
enable.
Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host controller
Wait Cycle Control (WCC) — RO. Hardwired to 0.
Parity Error Response (PER) — RO. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Hardwired to 0.
Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Hardwired to 0.
Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables the ICH6 to act as a master on the PCI bus for USB transfers.
Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory Space
registers.
0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F7:10h) for USB
I/O Space Enable (IOSE) — RO. Hardwired to 0.
receive a completion status other than “successful” for one of its DMA-initiated memory reads
on DMI (and subsequently on its internal interface).
2.0 should be programmed before this bit is set.
04
0000h
–
05h
(
EHC) is capable of generating (internally) SERR# when it
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W, RO
16 bits
529