NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 431

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

10.10.2
10.10.3
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
GPIO_USE_SEL—GPIO Use Select Register
Offset Address:
Default Value:
Lockable:
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address:
Default Value:
Lockable:
15:14,
31:29
11:9,
31:29
28:27
25:24
21:16
Bit
26,
5:0
15:0
Bit
26
GPIO_USE_SEL[31:29, 26, 15:14, 11:9, 5:0] — R/W. Each bit in this register enables the
corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1. The following bit is not implemented because there is no corresponding GPIO: 22.
2. The following bits are always 1 because they are unmultiplexed: 7, 8, 12:13, 19, 21, 23:25, 27:28
3. The following bits are not implemented because they are determined by the Desktop/Mobile
4. Bit 16 is not implemented because GPO selection will be controlled by Bit 0 (REQ/GNT pair)
5. Bit 17 is not implemented because GPO selection will be controlled by Bit 1 (REQ/GNT pair)
6. If GPIO[n] does not exist, then the bit in this register will always read as 0 and writes will have no
7. After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured
8. When configured to GPIO mode, the multiplexing logic should present the inactive state to native
Always 1. These GPIs are fixed as inputs.
GP_IO_SEL[28:27] — R/W. When set to a 1, the corresponding GPIO signal (if enabled in the
GPIO_USE_SEL register) is programmed as an input. When set to 0, the GPIO signal is
programmed as an output.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Always 1. This GPI is fixed as an input.
GP_IO_SEL[25:24] — R/W. When set to a 1, the corresponding GPIO signal (if enabled in the
GPIO_USE_SEL register) is programmed as an input. When set to 0, the GPIO signal is
programmed as an output.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Always 0. The GPOs are fixed as outputs.
Always 1. These GPIs are fixed as inputs.
configuration: 6, 18, 20
effect.
as their native function rather than as a GPIO. After just a PLTRST#, the GPIO in the core well
are configured as their native function.
logic that uses the pin as an input.
GPIOBASE + 00h
1BA83180h
No
GPIOBASE +04h
E400FFFFh
No
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
32-bit
Core for 0:7, 12, 16:21, 23,
26, 29:31
Resume for 8:11, 13:15, 25,
27, 28
R/W
32-bit
Resume
431