NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 155

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.14.4.1
5.14.4.2
Intel
Table 5-27. Causes of SMI# and SCI (Sheet 2 of 2)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
NOTES:
PCI Express* SCI
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using messages.
When a PME message is received, ICH6 will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is
also set, the ICH6 can cause an SCI via the GPE1_STS register.
PCI Express* Hot-Plug
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1 register. It
is also capable of generating an SMI. However, it is not capable of generating a wake event.
1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3. GBL_SMI_EN must be 1 to enable SMI.
4. EOS must be written to 1 to re-enable SMI for the next 1.
5. ICH6 must have SMI# fully enabled when ICH6 is also enabled to trap cycles. If SMI# is not enabled in
6. When a power button override first occurs, the system will transition immediately to S5. The SCI will only
7. Only GPI[15:0] may generate an SMI# or SCI.
BIOS_RLS written to
GBL_RLS written to
Write to B2h register
Periodic timer expires
64 ms timer expires
Enhanced USB Legacy Support
Event
Enhanced USB Intel Specific
Event
UHCI USB Legacy logic
Serial IRQ SMI reported
Device monitors match address in
its range
SMBus Host Controller
SMBus Slave SMI message
SMBus SMBALERT# signal active
SMBus Host Notify message
received
(Mobile Only) BATLOW# assertion
Access microcontroller 62h/66h
SLP_EN bit written to 1
conjunction with the trap enabling, then hardware behavior is undefined.
occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting
SCI_EN.
Cause
1-5
SCI
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
SMI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
GBL_EN=1
BIOS_EN=1
APMC_EN = 1
PERIODIC_EN=1
SWSMI_TMR_EN=1
LEGACY_USB2_EN = 1
INTEL_USB2_EN = 1
LEGACY_USB_EN=1
none
none
SMB_SMI_EN
Host Controller Enabled
none
none
HOST_NOTIFY_INTREN
BATLOW_EN=1.
MCSMI_EN
SMI_ON_SLP_EN=1
Additional Enables
Functional Description
GBL_STS
BIOS_STS
APM_STS
PERIODIC_STS
SWSMI_TMR_STS
LEGACY_USB2_STS
INTEL_USB2_STS
LEGACY_USB_STS
SERIRQ_SMI_STS
DEVMON_STS,
DEVACT_STS
SMBus host status reg.
SMBus_SMI_STS
SMBus_SMI_STS
SMBus_SMI_STS
HOST_NOTIFY_STS
BATLOW_STS
MCSMI_STS
SMI_ON_SLP_EN_STS
Where Reported
155