NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 658

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
18.2.11
18.2.12
658
®
High Definition Audio Controller Registers (D27:F0)
INTSTS—Interrupt Status Register
(Intel
Memory Address: HDBAR + 24h
Default Value:
WALCLK—Wall Clock Counter Register
(Intel
Memory Address: HDBAR + 30h
Default Value:
29:8
31:0
Bit
7:0
Bit
31
30
®
®
Global Interrupt Status (GIS) — RO. This bit is an OR of all the interrupt status bits in this register.
NOTE: This bit is not affected by the D3
Controller Interrupt Status (CIS) — RO. Status of general controller interrupt.
1 = Indicates that an interrupt condition occurred due to a Response Interrupt, a Response Buffer
NOTES:
Reserved
Stream Interrupt Status (SIS) — RO.
1 = Indicates that an interrupt condition occurred on the corresponding stream. This bit is an OR of
NOTE: These bits are set regardless of the state of the corresponding interrupt enable bits.
The streams are numbered and the SIE bits assigned sequentially, based on their order in the
register set.
Bit 0: input stream 1
Bit 1: input stream 2
Bit 2: input stream 3
Bit 3: input stream 4
Bit 4: output stream 1
Bit 5: output stream 2
Bit 6: output stream 3
Bit 7: output stream 4
Wall Clock Counter — RO. 32 bit counter that is incremented on each link BCLK period and rolls
over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0 with a period of approximately
179 seconds.
This counter is enabled while the BCLK bit is set to 1. Software uses this counter to synchronize
between multiple controllers. Will be reset on controller reset.
1. This bit is set regardless of the state of the corresponding interrupt enable bit, but a hardware
2. This bit is not affected by the D3
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
interrupt will not be generated unless the corresponding enable bit is set.
Overrun Interrupt, or a SDIN state change event. The exact cause can be determined by
interrogating other registers. This bit is an OR of all of the stated interrupt status bits for this
register.
all of the stream’s interrupt status bits.
00000000h
00000000h
HOT
Intel
to D0 transition.
HOT
Description
Description
®
to D0 transition.
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
32 bits
32 bits
RO
RO