NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 138

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.10
5.10.1
5.10.2
138
Table 5-15. APIC Interrupt Mapping (Sheet 1 of 2)
Advanced Programmable Interrupt Controller
(APIC) (D31:F0)
In addition to the standard ISA-compatible PIC described in the previous chapter, the ICH6
incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor
system, APIC can be used in either a uni-processor or multi-processor system.
Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:
Interrupt Mapping
The I/O APIC within the ICH6 supports 24 APIC interrupts. Each interrupt has its own unique
vector assigned by software. The interrupt vectors are mapped as follows, and match “Config 6” of
the Multi-Processor Specification.
•
•
•
•
IRQ #
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Method of Interrupt Transmission. The I/O APIC transmits interrupts through memory
writes on the normal datapath to the processor, and interrupts are handled without the need for
the processor to run an interrupt acknowledge cycle.
Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt
number. For example, interrupt 10 can be given a higher priority than interrupt 3.
More Interrupts. The I/O APIC in the ICH6 supports a total of 24 interrupts.
Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O APIC
devices in the system with their own interrupt vectors.
SERIRQ
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Via
No
No
No
No
Direct from
Yes
Pin
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
1
Message
Via PCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Intel
Cascade from 8259 #1
8254 Counter 0, HPET #0 (legacy mode)
RTC, HPET #1 (legacy mode)
Option for SCI, TCO
Option for SCI, TCO
HPET #2, Option for SCI, TCO
FERR# logic
IDEIRQ (legacy mode, non-combined or combined
mapped as primary), SATA Primary (legacy mode)
IDEIRQ (legacy mode — combined, mapped as
secondary), SATA Secondary (legacy mode)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Internal Modules