NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 390

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.7
10.7.1
390
Table 10-8. Processor Interface PCI Register Address Map (LPC I/F—D31:F0)
Processor Interface Registers (LPC I/F—D31:F0)
Table 10-8
NMI_SC—NMI Status and Control Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
61h
70h
92h
F0h
CF9h
Offset
Bit
7
6
5
4
3
2
1
0
SERR# NMI Source Status (SERR#_NMI_STS) — RO.
1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and if bit 2
NOTE: This bit is set by any of the ICH6 internal sources of SERR; this includes SERR assertions
IOCHK# NMI Source Status (IOCHK_NMI_STS) — RO.
1 = Bit is set if an LPC agent (via SERIRQ) asserted IOCHK# and if bit 3 (IOCHK_NMI_EN) is
Timer Counter 2 OUT Status (TMR2_OUT_STS) — RO. This bit reflects the current state of the
8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a
determinate value. When writing to port 61h, this bit must be a 0.
Refresh Cycle Toggle (REF_TOGGLE) — RO. This signal toggles from either 0 to 1 or 1 to 0 at a
rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be
a 0.
IOCHK# NMI Enable (IOCHK_NMI_EN) — R/W.
0 = Enabled.
1 = Disabled and cleared.
PCI SERR# Enable (PCI_SERR_EN) — R/W.
0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared.
Speaker Data Enable ( SPKR_DAT_EN) — R/W.
0 = SPKR output is a 0.
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Timer Counter 2 Enable (TIM_CNT2_EN) — R/W.
0 = Disable
1 = Enable
is the register address map for the processor interface registers.
NMI_SC
NMI_EN
PORT92
COPROC_ERR
RST_CNT
(PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2 to 0. To reset the
interrupt, set bit 2 to 1 and then set it to 0. When writing to port 61h, this bit must be 0.
cleared. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 1
and then set it to 0. When writing to port 61h, this bit must be a 0.
Mnemonic
forwarded from the secondary PCI bus, errors on a PCI Express* port, or other internal
functions that generate SERR#.
61h
00h
No
NMI Status and Control
NMI Enable
Fast A20 and Init
Coprocessor Error
Reset Control
Register Name
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
00h
80h
00h
00h
00h
Core
R/W, RO
8-bit
Default
WO
R/W, RO
R/W (special)
R/W
R/W
Type