NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 589
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NH82801FBM S L89K
Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet
1.NH82801FBM_S_L89K.pdf
(786 pages)
Specifications of NH82801FBM S L89K
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Compliant
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16.1.15
T
16.1.16
16.1.17
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
SID—Subsystem Identification Register (Audio—D30:F2)
Address Offset:
Default Value:
Lockable:
The SID register, in combination with the Subsystem Vendor ID register (D30:F2:2Ch) make it
possible for the operating environment to distinguish one audio subsystem from the other(s).
This register is implemented as write-once register. Once a value is written to it, the value can be
read back. Any subsequent writes will have no effect.
This register is not affected by the D3
CAP_PTR—Capabilities Pointer Register (Audio—D30:F2)
Address Offset:
Default Value:
Lockable:
This register indicates the offset for the capability pointer.
INT_LN—Interrupt Line Register (Audio—D30:F2)
Address Offset:
Default Value:
Lockable:
This register indicates which PCI interrupt line is used for the AC ’97 module interrupt.
15:0
Bit
Bit
7:0
Bit
7:0
Subsystem ID — R/WO.
Capabilities Pointer (CAP_PTR) — RO. This field indicates that the first capability pointer offset is
offset 50h
Interrupt Line (INT_LN) — R/W. This data is not used by the Intel
to software the interrupt line that the interrupt pin is connected to.
2E
0000h
No
34h
50h
No
3Ch
00h
No
–
2Fh
HOT
to D0 transition.
AC ’97 Audio Controller Registers (D30:F2)
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
ICH6. It is used to communicate
R/WO
16 bits
Core
RO
8 bits
Core
R/W
8 bits
Core
589
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