NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 73

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

2.21
Intel
Table 2-21. Power and Ground Signals (Sheet 1 of 2)
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Power and Ground
(Mobile Only)
(Mobile Only)
VccUSBPLL
V5REF_Sus
VccLAN3_3
VccLAN1_5
VccDMIPLL
VccSus3_3
VccSus1_5
Vcc1_5_A
Vcc1_5_B
VccRTC
Vcc3_3
Vcc2_5
V5REF
Name
3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3, S4, S5 or
G3 states.
1.5 V supply for core well logic, group A (52 pins). This power may be shut off in S3, S4, S5
or G3 states.
1.5 V supply for core well logic, group B (45 pins). This power may be shut off in S3, S4, S5
or G3 states.
2.5 V supply for internal logic (2 pins). This power may be shut off in S3, S4, S5 or G3
states.
NOTE: This voltage may be generated internally (see
Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut off in S3,
S4, S5 or G3 states.
3.3 V supply for resume well I/O buffers (20 pins). This power is not expected to be shut off
unless the system is unplugged in desktop configurations or the main battery is removed or
completely drained and AC power is not available in mobile configurations.
1.5 V supply for resume well logic (3 pin). This power is not expected to be shut off unless
the system is unplugged in desktop configurations or the main battery is removed or
completely drained and AC power is not available in mobile configurations.
This voltage may be generated internally (see
generated internally, these pins should not be connected to an external supply.
Reference for 5 V tolerance on resume well inputs (1 pin). This power is not expected to be
shut off unless the system is unplugged in desktop configurations or the main battery is
removed or completely drained and AC power is not available in mobile configurations.
3.3 V supply for LAN Connect interface buffers (4 pins). This is a separate power plane that
may or may not be powered in S3–S5 states depending upon the presence or absence of
AC power and network connectivity. This plane must be on in S0 and S1.
NOTE: In Desktop mode these signals are added to the VccSus3_3 group.
1.5 V supply for LAN controller logic (2 pins). This is a separate power plane that may or
may not be powered in S3–S5 states depending upon the presence or absence of AC
power and network connectivity. This plane must be on in S0 and S1.
NOTES:
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This power is not
expected to be shut off unless the RTC battery is removed or completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull
1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This power may
be shut off in S3, S4, S5 or G3 states. Must be powered even if USB not used.
1.5 V supply for core well logic (1 pins). This signal is used for the DMI PLL. This power may
be shut off in S3, S4, S5 or G3 states.
1. This voltage will be generated internally if VccSus1_5 is generated internally (see
2. In Desktop mode these signals are added to the VccSus1_5 group.
Section 2.22.1
connected to an external supply.
If generated internally, these pins should not be connected to an external supply.
VccRTC low. Clearing CMOS in an ICH6-based platform can be done by using a
jumper on RTCRST# or GPI.
for strapping option). If generated internally, these pins should not be
Description
Section 2.22.1
Section 2.22.1
for strapping option). If
Signal Description
for strapping option).
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