NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 650

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Intel
650
Table 18-2. Intel
®
High Definition Audio Controller Registers (D27:F0)
(Intel
D27:F0) (Sheet 2 of 4)
HDBAR +
AC–ADh
8C–8Dh
A8–ABh
AE–AFh
B8–BBh
5A–5Bh
9C–9Fh
A0–A2h
A4–A7h
B0–B1h
B2–B3h
88–8Bh
98–9Bh
50–53h
54–57h
58–59h
60–63h
64–67h
68–69h
70–73h
74–77h
80–82h
84–87h
90–91h
92–93h
8E–8F
Offset
4Dh
5Ch
5Dh
4Eh
5Eh
83h
A3h
®
®
High Definition Audio
High Definition Audio PCI Register Address Map
RIRBUBASE
RIRBLBASE
ISD0FIFOW
ISD1FIFOW
CORBSIZE
ISD0FIFOS
ISD1FIFOS
ISD0BDPU
Mnemonic
ISD0BDPL
ISD1BDPL
DPUBASE
RIRBSIZE
DPLBASE
RINTCNT
ISD0LPIB
ISD1LPIB
RIRBCTL
RIRBSTS
ISD0FMT
ISD1FMT
CORBST
ISD0CTL
ISD0STS
ISD0CBL
ISD1CTL
ISD1STS
ISD1CBL
RIRBWP
ISD0LVI
ISD1LVI
IRS
IC
IR
CORB Status
CORB Size
RIRB Lower Base Address
RIRB Upper Base Address
RIRB Write Pointer
Response Interrupt Count
RIRB Control
RIRB Status
RIRB Size
Immediate Command
Immediate Response
Immediate Command Status
DMA Position Lower Base Address
DMA Position Upper Base Address
Input Stream Descriptor 0 (ISD0) Control
ISD0 Status
ISD0 Link Position in Buffer
ISD0 Cyclic Buffer Length
ISD0 Last Valid Index
ISD0 FIFO Watermark
ISD0 FIFO Size
ISD0 Format
ISD0 Buffer Descriptor List Pointer-Lower Base
Address
ISD0 Buffer Description List Pointer-Upper
Base Address
Input Stream Descriptor 1(ISD01) Control
ISD1 Status
ISD1 Link Position in Buffer
ISD1 Cyclic Buffer Length
ISD1 Last Valid Index
ISD1 FIFO Watermark
ISD1 FIFO Size
ISD1 Format
ISD1 Buffer Descriptor List Pointer-Lower Base
Address
Register Name
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
040000h
040000h
Default
0000h
0000h
0000h
0000h
0004h
0077h
0000h
0000h
0004h
0077h
0000h
00h
42h
00h
00h
42h
00h
00h
R/W, R/WC
R/WC, RO
R/WC, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
Access
R/WC
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO