NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 34

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Contents
Figures
34
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2-1 Intel
2-2 Intel
2-3 Example External RTC Circuit .................................................................................................... 76
4-1 Desktop Conceptual System Clock Diagram.............................................................................. 96
4-2 Mobile Conceptual Clock Diagram ............................................................................................. 96
5-1 Generation of SERR# to Platform ............................................................................................ 103
5-2 64-Word EEPROM Read Instruction Waveform....................................................................... 110
5-3 LPC Interface Diagram ............................................................................................................. 116
5-4 Intel
5-5 DMA Request Assertion through LDRQ# ................................................................................. 124
5-6 Coprocessor Error Timing Diagram .......................................................................................... 148
5-7 Physical Region Descriptor Table Entry ................................................................................... 181
5-8 SATA Power States.................................................................................................................. 189
5-9 USB Legacy Keyboard Flow Diagram ...................................................................................... 199
5-10 Intel
5-11 Intel
5-12 AC ’97 2.3 Controller-Codec Connection ................................................................................. 229
5-13 AC-Link Protocol....................................................................................................................... 230
5-14 AC-Link Powerdown Timing ..................................................................................................... 231
5-15 SDIN Wake Signaling ............................................................................................................... 232
5-16 Intel
21-1 Intel
21-2 Intel
22-1 Clock Timing............................................................................................................................. 759
22-2 Valid Delay from Rising Clock Edge ......................................................................................... 759
22-3 Setup and Hold Times .............................................................................................................. 759
22-4 Float Delay ............................................................................................................................... 760
22-5 Pulse Width .............................................................................................................................. 760
22-6 Output Enable Delay ................................................................................................................ 760
22-7 IDE PIO Mode .......................................................................................................................... 761
22-8 IDE Multiword DMA .................................................................................................................. 761
22-9 Ultra ATA Mode (Drive Initiating a Burst Read) ........................................................................ 762
22-10Ultra ATA Mode (Sustained Burst).......................................................................................... 762
22-11Ultra ATA Mode (Pausing a DMA Burst)................................................................................. 763
22-12Ultra ATA Mode (Terminating a DMA Burst)........................................................................... 763
22-13USB Rise and Fall Times........................................................................................................ 764
22-14USB Jitter................................................................................................................................ 764
22-15USB EOP Width...................................................................................................................... 764
22-16SMBus Transaction................................................................................................................. 765
22-17SMBus Timeout ...................................................................................................................... 765
22-18Power Sequencing and Reset Signal Timings (Desktop Only)............................................... 766
22-19Power Sequencing and Reset Signal Timings (Mobile Only) ................................................. 767
22-20G3 (Mechanical Off) to S0 Timings (Desktop Only)................................................................ 768
22-21G3 (Mechanical Off) to S0 Timings (Mobile Only) .................................................................. 769
22-22S0 to S1 to S0 Timing ............................................................................................................. 769
22-23S0 to S5 to S0 Timings, S3
22-24S0 to S5 to S0 Timings, S3
Desktop Configuration ................................................................................................................ 42
Mobile Configuration................................................................................................................... 42
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ICH6 Interface Signals Block Diagram (Desktop)............................................................. 54
ICH6-M Interface Signals Block Diagram (Mobile Only)................................................... 55
ICH6 DMA Controller ...................................................................................................... 121
ICH6-Based Audio Codec ’97 Specification, Version 2.3 ............................................... 227
High Definition Audio Link Protocol Example ................................................................. 234
ICH6 Preliminary Ballout (Topview–Left Side)................................................................ 724
ICH6 Preliminary Ballout (Topview–Right Side) ............................................................. 725
ICH6-USB Port Connections ......................................................................................... 206
COLD
HOT
(Desktop Only)...................................................................... 771
(Desktop Only)..................................................................... 770
Intel
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I/O Controller Hub 6 (ICH6) Family Datasheet