NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 118

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Functional Description
5.5.1.3
5.5.1.4
118
Table 5-6. Cycle Type Bit Definitions
Table 5-7. Transfer Size Bit Definition
SIZE
Cycle Type / Direction (CYCTYPE + DIR)
The ICH6 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0.
Bits[3:2] are reserved. The ICH6 always drives them to 00. Peripherals running bus master cycles
are also supposed to drive 00 for bits 3:2; however, the ICH6 ignores those bits. Bits[1:0] are
encoded as listed in
Bits[3:2]
Bits[1:0]
00
00
01
01
10
10
11
00
01
10
11
Bit1
Table 5-6
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel
master cycle drives this combination, the ICH6 may abort the transfer.
32-bit transfer (4 bytes)
0
1
0
1
0
1
x
Table
I/O Read
I/O Write
Memory Read
Memory Write
DMA Read
DMA Write
Reserved. If a peripheral performing a bus master cycle generates this value, the
Intel
shows the valid bit encodings.
5-7.
®
ICH6 aborts the cycle.
®
ICH6 never drives this combination. If a peripheral running a bus
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Size
Definition