NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 33

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

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Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
High Precision Event Timer Registers
20.1
Ballout Definition
Electrical Characteristics
22.1
22.2
22.3
22.4
22.5
Package Information
Testability
24.1
24.2
19.1.58 AECC — Advanced Error Capabilities and Control Register
19.1.59 RES — Root Error Status Register
19.1.60 RCTCL — Root Complex Topology Capability List Register
19.1.61 ESD — Element Self Description Register
19.1.62 ULD — Upstream Link Description Register
19.1.63 ULBA — Upstream Link Base Address Register
19.1.64 PCIECR1 — PCI Express Configuration Register 1
19.1.65 PCIECR2 — PCI Express Configuration Register 2
Memory Mapped Registers...............................................................................................716
20.1.1 GCAP_ID—General Capabilities and Identification Register...............................717
20.1.2 GEN_CONF—General Configuration Register....................................................717
20.1.3 GINTR_STA—General Interrupt Status Register ................................................718
20.1.4 MAIN_CNT—Main Counter Value Register.........................................................718
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register .........................719
20.1.6 TIMn_COMP—Timer n Comparator Value Register............................................721
Thermal Specifications .....................................................................................................733
Absolute Maximum Ratings ..............................................................................................733
DC Characteristics ............................................................................................................734
AC Characteristics ............................................................................................................743
Timing Diagrams...............................................................................................................759
XOR Chain Test Mode Description...................................................................................779
24.1.1 XOR Chain Testability Algorithm Example ..........................................................780
XOR Chain Tables ............................................................................................................781
...............................................................................................................................779
(PCI Express—D28:F0/F1/F2/F3)........................................................................711
(PCI Express—D28:F0/F1/F2/F3)........................................................................711
(PCI Express—D28:F0/F1/F2/F3)........................................................................711
(PCI Express—D28:F0/F1/F2/F3)........................................................................712
(PCI Express—D28:F0/F1/F2/F3)........................................................................712
(PCI Express—D28:F0/F1/F2/F3)........................................................................713
(PCI Express—D28:F0/F1/F2/F3)........................................................................713
(PCI Express—D28:F0/F1/F2/F3)........................................................................713
.................................................................................................................723
..........................................................................................................777
.................................................................................................733
........................................................................715
Contents
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