NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 596

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

AC ’97 Audio Controller Registers (D30:F2)
16.2.1
596
Note: Internal reset as a result of D3
registers shared with the AC ’97 Modem (GCR, GSR, CASR). All resume well registers will not be
reset by the D3
Core well registers and bits not reset by the D3
Resume well registers and bits will not be reset by the D3
x_BDBAR—Buffer Descriptor Base Address Register
(Audio—D30:F2)
I/O Address:
Default Value:
Lockable:
Software can read the register at offset 00h by performing a single 32-bit read from address offset
00h. Reads across DWord boundaries are not supported.
•
•
•
•
31:3
Bit
2:0
offset 2Ch
offset 30h
offset 34h – Codec Access Semaphore Register (CAS)
offset 30h
Buffer Descriptor Base Address[31:3] — R/W. These bits represent address bits 31:3. The data
should be aligned on 8-byte boundaries. Each buffer descriptor is 8 bytes long and the list can
contain a maximum of 32 entries.
Hardwired to 0.
–
–
–
HOT
33h – bits [29,15,11:10,0] Global Status (GLOB_STA)
33h – bits [17:16] Global Status (GLOB_STA)
2Fh – bits 6:0 Global Control (GLOB_CNT)
NABMBAR + 00h (PIBDBAR), Attribute:
NABMBAR + 10h (POBDBAR),
NABMBAR + 20h (MCBDBAR)
MBBAR + 40h (MC2BDBAR)
MBBAR + 50h (PI2BDBAR)
MBBAR + 60h (SPBAR)
00000000h
No
to D0 transition.
HOT
to D0 transition will reset all the core well registers except the
Intel
HOT
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Size:
Power Well:
to D0 transition:
HOT
to D0 transition:
32 bits
Core
R/W