NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 88

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

Pin States
88
Table 3-4. Power Plane and States for Output and I/O Signals for Mobile Configurations
ACZ_BIT_CLK
Signal Name
ACZ_SDOUT
GPIO[28:27]
GPIO[34:33]
ACZ_SYNC
ACZ_RST#
GPIO[24]
GPIO[25]
GPO[19]
GPO[21]
GPO[23]
NOTES:
10.SLP_S5# signals will be high in the S4 state.
12.PETp/n[4:1] high until port is enabled by software.
13.In S3
11.Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time
(Sheet 4 of 4)
1. ICH6 drives these signals Low before PWROK rising and High after the processor reset.
2. GPIO[18] will toggle at a frequency of approximately 1 Hz when the ICH6 comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the ICH6’s VRMPWRGD and PWROK
4. LAN Connect and EEPROM signals will either be “Defined” or “Off” in S3-S5 states depending upon whether
5. The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled or low if it is
6. The states of Vcc3_3 signals are taken at the times during PLTRST# and Immediately after PLTRST#.
7. The states of VccSus3_3 signals are taken at the times during RSMRST# and Immediately after RSMRST#.
8. ICH6 drives these signals Low before PWROK rising and Low after the processor reset.
9. GPIO[25] transitions from pulled high internally to actively driven following the de-assertion of the RSMRST#
signals, and thus will be driven low by ICH6 when either VRMPWRGD or PWROK are inactive. During boot,
or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z.
or not the LAN power planes are active.
disabled.
pin.
ACZ_RST# will be High and ACZ_BIT_CLK will be Running.
may be powered when the ICH6 is in the S3
HOT
, signal states are platform implementation specific, as some external components and interfaces
VccSus3_3
VccSus3_3
VccSus3_3
VccSus3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Vcc3_3
Power
Plane
Internal Pull-
Internal Pull-
Internal Pull-
PLTRST#
RSMRST#
High-Z with
High-Z with
High-Z with
During
Intel High Definition Audio Interface
down
down
down
High
High
High
High
High
High
Low
Low
Unmultiplexed GPIO Signals
6
7
/
after PLTRST#
Immediately
HOT
RSMRST#
Running
Running
Intel
Low
Low
High9
High
High
High
High
High
Low
state.
11
11
®
I/O Controller Hub 6 (ICH6) Family Datasheet
7
6
/
Running
Running
Running
Defined
Defined
Defined
Defined
Defined
Defined
Defined
C3/C4
High
Defined
Defined
Defined
Defined
Defined
Defined
Defined
TBD
Low
Low
Low
S1
S3
Defined
Defined
Defined
COLD
Low
Off
Off
Off
Off
Off
Off
Off
13
Defined
Defined
Defined
S4/S5
Low
Off
Off
Off
Off
Off
Off
Off