NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 482

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NH82801FBM S L89K

Manufacturer Part Number
NH82801FBM S L89K
Description
Manufacturer
Intel
Datasheet

Specifications of NH82801FBM S L89K

Lead Free Status / RoHS Status
Compliant
SATA Controller Registers (D31:F2)
12.1.44
12.1.45
482
BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)
Address Offset:
Default Value:
BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset:
Default Value:
Bits
31:0
Bits
31:0
BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form the contents of
the second DWord of any BIST FIS initiated by the ICH6. This register is not port specific — its
contents will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST
FIS are only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit mode”,
this register’s contents will be transmitted as the BIST FIS 2nd DW regardless of whether or not the
“T” bit is indicated in the BFCS register (D31:F2:E0h).
BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form the contents of
the third DWord of any BIST FIS initiated by the ICH6. This register is not port specific — its contents
will be used for BIST FIS initiated on any port. Although the 2nd and 3rd DWs of the BIST FIS are
only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit mode”, this
register’s contents will be transmitted as the BIST FIS 3rd DW regardless of whether or not the “T” bit
is indicated in the BFCS register (D31:F2:E0h).
E4h
00000000h
E8h
00000000h
E7h
EBh
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
32 bits
32 bits
R/W
R/W

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