NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 360

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.1.26
360
BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
5:4
Bit
7:2
Bit
6
3
2
1
0
1
0
Reserved
BIOS Lock Enable (BLE) — R/WLO.
0 = Setting the BIOSWE will not cause SMIs.
1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be cleared by a
BIOS Write Enable (BIOSWE) — R/W.
0 = Only read cycles result in Firmware Hub I/F cycles.
1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written
FWH_Legacy_E_EN — R/W. This bit enables the decoding of the legacy 128-K range at E0000h –
EFFFFh.
0 = Disable.
1 = Enable the following legacy ranges for the Firmware Hub
Reserved
FWH_70_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FWH_60_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FWH_50_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
FWH_40_EN — R/W. This bit enables decoding two 1-M Firmware Hub memory ranges.
0 = Disable.
1 = Enable the following ranges for the Firmware Hub
PLTRST#
from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is generated. This ensures
that only SMI code can update BIOS.
E0000h – EFFFFh
FF70 0000h – FF7F FFFFh
FF30 0000h – FF3F FFFFh
FF60 0000h – FF6F FFFFh
FF20 0000h – FF2F FFFFh
FF50 0000h – FF5F FFFFh
FF10 0000h – FF1F FFFFh
FF40 0000h – FF4F FFFFh
FF00 0000h – FF0F FFFFh
DCh
00h
No
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
Core
R/WLO, R/W
8 bit