NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 442

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

IDE Controller Registers (D31:F1)
11.1.8
11.1.9
11.1.10
11.1.11
.
442
BCC—Base Class Code Register (IDE—D31:F1)
CLS—Cache Line Size Register (IDE—D31:F1)
Address Offset:
Default Value:
Address Offset:
Default Value:
PMLT—Primary Master Latency Timer Register
(IDE—D31:F1)
Address Offset:
Default Value:
PCMD_BAR—Primary Command Block Base Address
Register (IDE—D31:F1)
Address Offset:
Default Value:
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
31:16
15:3
Bit
2:1
Bit
7:0
Bit
7:0
Bit
7:0
0
Reserved
Base Address — R/W. Base address of the I/O space (8 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE) — RO. Hardwired to 1 indicating a request for I/O space.
Base Class Code (BCC) — RO.
01 = Mass storage device
Cache Line Size (CLS) — RO.
00h = Hardwired. The IDE controller is implemented internally so this register has no meaning.
Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The IDE controller is implemented internally, and is not arbitrated as a PCI device,
so it does not need a Master Latency Timer.
0Bh
01h
0Ch
00h
0Dh
00h
10h
00000001h
–
13h
Intel
Description
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
R/W, RO
32 bits
RO
8 bits