MC68376BAMFT20 Freescale Semiconductor, MC68376BAMFT20 Datasheet - Page 206

• Manufacturer Part Number: MC68376BAMFT20
• Manufacturer: Freescale Semiconductor

Specifications of MC68376BAMFT20

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Interface Type: QSPI/SCI
• Program Memory Type: ROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 7.5KB
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• On-chip Adc: 16-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 160
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

8.12.4 QADC Clock (QCLK) Generation
8-24
MOTOROLA
PRESCALER RATE SELECTION
SYSTEM CLOCK (f
QUEUE 2 MODE RATE SELECTION
Figure 8-8 is a block diagram of the clock subsystem. QCLK provides the timing for
the A/D converter state machine which controls the timing of conversions. QCLK is
also the input to a 17-stage binary divider which implements the periodic/interval timer.
To obtain the specified analog conversion accuracy, the QCLK frequency (f
be within the tolerance specified in Table A-13.
Before using the QADC, software must initialize the prescaler with values that put
QCLK within a specified range. Though most applications initialize the prescaler once
and do not change it, write operations to the prescaler fields are permitted.
HIGH TIME CYCLES (PSH)
LOW TIME CYCLES (PSL)
ADD HALF CYCLE TO HIGH (PSA)
(FROM QACR0):
INPUT SAMPLE TIME (FROM CCW)
(FROM QACR2):
sys
A change in the prescaler value while a conversion is in progress is
likely to corrupt the conversion result. Therefore, any prescaler write
operation should be done only when both queues are disabled.
)
Figure 8-8 QADC Clock Subsystem Functions
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE
5
DOWN COUNTER
5-BIT
ONE'S COMPLEMENT
COMPARE
3
4
3
DETECT
ZERO
5
3
2 7
2 8
LOAD PSH
2 9
2 10
PERIODIC/INTERVAL
CAUTION
BINARY COUNTER
A/D CONVERTER
STATE MACHINE
TIMER SELECT
2 11
2 12
2 13
2 14
RESET QCLK
SET QCLK
2 15
2 16 2 17
GENERATE
CLOCK
QADC CLOCK
( 2 TO 40 )
USER’S MANUAL
SAR CONTROL
SAR[9:0]
QCLK
PERIODIC/INTERVAL
TRIGGER EVENT
MC68336/376
QCLK
QADC CLOCK BLOCK
) must